1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device provided with an internal stepdown circuit for stepping down a supply voltage applied from an external power supply.
2. Description of the Prior Art
In semiconductor memory devices such as dynamic random access memories (DRAMs) and static random access memories (SRAMs), reduction in size has been done to improve the degree of integration, and thus sizes of transistors have been extremely reduced. For instance, DRAMs of 16M bits or SRAMs of 4M bits have used the transistors in the order of 0.5 .mu.m. However, if such small transistors were used under a standard supply voltage of 5 V, an excessive electric field would be applied to the transistors, and thus a reliability would not be ensured due to problems such as hot electrons.
Accordingly, there has been such attempts that an internal stepdown circuit is arranged in the semiconductor integrated circuit device so as to step down an external voltage by the internal stepdown circuit before it is supplied to internal circuits, and thus to reduce the electric field applied to the minute transistors.
FIG. 5 is a circuit diagram illustrating a conventional internal stepdown circuit disclosed, for instance, in "A New On-Chip Voltage Converter for Submicrometer High-Density DRAM's" (Journal of Solid-State Circuits, Vol.SC-22, No. 3, June 1987, pp. 437-441). The illustrated internal stepdown circuit essentially consists of a reference voltage generator circuit 1 and an internal voltage correcting circuit 2. The reference voltage generator circuit 1 is adapted to generate a reference voltage V.sub.REF with respect to the internal voltage correcting circuit 2, and include P-type MOS transistors (will be called as "PMOS transistors" hereinafter) 1a-1e. The PMOS transistors 1a-1c are connected in series to each other and are interposed between a supply input terminal 3 and the ground GND. Specifically, the PMOS transistor 1a has a source connected to the supply input terminal 3. The PMOS transistor 1b has a source connected to a drain of the PMOS transistor 1a. The PMOS transistor 1c has a source connected to a drain of the PMOS transistor 1b. The PMOS transistor 1c has a drain connected to the ground GND. The PMOS transistor 1a has a gate connected to a source of the PMOS transistor 1b. The PMOS transistor 1b has a gate connected to a source of the PMOS transistor 1c. The PMOS transistor 1c has a gate connected to the ground GND. Thus, these PMOS transistors 1a-1c are used as resistors, respectively, and constitute a resistive potential divider circuit. The supply input terminal 3 receives a supply voltage Ext.vcc from an external power supply (not shown). Other PMOS transistors 1d and 1e are connected in series to each other, and are interposed between the supply input terminal 3 and the ground GND in parallel to the above PMOS transistors 1a-1c. Specifically, the PMOS transistor 1d has a source connected to the supply input terminal 3 and the PMOS transistor 1e has a source connected to a drain of the PMOS transistor 1d. The drain of the PMOS transistor 1e is connected to the ground GND. The gate of the PMOS transistor 1d is connected to the drain of the PMOS transistor 1b and the source of the PMOS transistor 1c. The gate of the PMOS transistor 1e is connected to the ground GND.
The internal voltage correcting circuit 2 is adapted to correct an internal voltage V.sub.INT based on the reference voltage V.sub.REF so as to prevent the fluctuation of the internal voltage V.sub.INT which may be caused by the fluctuation of the supply voltage Ext.Vcc, and is formed of a current quantity switching circuit 21, a voltage comparator circuit 22 and an output transistor 23. The current quantity switching circuit 21 is adapted to switch a current quantity supplied to the voltage comparator circuit 22 in accordance with switching between an active mode and a standby mode of the semiconductor integrated circuit device, and is formed of two PMOS transistors 21a and 21b interposed in parallel between the supply input terminal 3 and the voltage comparator circuit 22. The PMOS transistor 21a has a source connected to the supply input terminal 3 and a gate for receiving a clock signal .phi.. The PMOS transistor 21b has a source connected to the supply input terminal 3 and a gate connected to the ground GND. The voltage comparator circuit 22 is adapted to make a comparison between the reference voltage V.sub.REF applied from the reference voltage generator circuit 1 and the internal voltage V.sub.INT supplied from the output transistor 23 and to control a conductivity of the output transistor 23 in accordance with a result of the comparison, and is formed of two PMOS transistor 22a and 22b and two N-channel MOS transistors (will be called as "NMOS transistors" hereinafter) 22c and 22d. The PMOS transistor 22a has a source connected to the drains of the PMOS transistors 21a and 21b, a drain connected to a drain of the PMOS transistor 22c and a gate connected to the drain of the PMOS transistor 1d and the source of the PMOS transistor 1e. The PMOS transistor 22b has a source connected to the drains of the PMOS transistors 21a and 21b, a drain connected to a drain of the NMOS transistor 22d and a gate connected to the source of the output transistor 23. Sources of the NMOS transistors 22c and 22d are connected to the ground GND. Gates of the NMOS transistors 22c and 22d are commonly connected to the drain of the PMOS transistor 22b. Further, the drains of the PMOS transistor 22a and the NMOS transistor 22c are connected to the gate of the output transistor 23. The output transistor 23 is formed of a PMOS transistor of which source is connected to the supply input terminal 3.
The internal stepdown circuit of the prior art shown in FIG. 5 operates as follows.
First, operations of the reference voltage generator circuit 1 will be described below. The PMOS transistors 1a-1c are in resistance connection and are interposed between the supply input terminal 3 and the ground GND, so that a node P between the drain of the PMOS transistor 1b and the source of the PMOS transistor 1c has a potential of Ext.Vcc-2.times..vertline.V.sub.TP .vertline., in which V.sub.TP is a threshold voltage of the PMOS transistor. Since the node P is also connected to the gate of the PMOS transistor 1d, the potential at the node P is also a gate potential in the PMOS transistor 1d. Therefore, a potential difference between the source and drain of the PMOS transistor 1d is not affected by the fluctuation of the supply voltage Ext.Vcc and always kept at a constant value (=2.times..vertline.V.sub.TP .vertline.). Thus, a saturation current Id flowing in the PMOS transistor 1d is always kept constant. However, this saturation current Id does not flow into the voltage comparator circuit 22 and thus is entirely supplied to the PMOS transistor 1e. Accordingly, the current Ie flowing in this PMOS transistor le is always constant (Ie=Id). Since the potential at the drain of the PMOS transistor 1e is fixed to the ground potential of 0 V(zero volt), the potential at the source of the PMOS transistor le has a constant value (=V.sub.REF) if the current Ie is constant. Therefore, the reference voltage generator circuit 1 will always generate the constant reference voltage V.sub.REF.
Operations of the internal voltage correcting circuit 2 will be described below. When the semiconductor integrated circuit device provided with the internal stepdown circuit in FIG. 5 is in an active mode, the clock signal .phi. is at an "L" level. Therefore, the PMOS transistor 21a is kept ON in the active mode. Meanwhile, the PMOS transistor 21b is always in the ON state because its gate is connected to the ground GND. Therefore, both the PMOS transistors 21a and 21b are turned on in the active mode, and thus a large current is supplied to the voltage comparator circuit 22. The voltage comparator circuit 22 compares the reference voltage V.sub.REF with the internal voltage V.sub.INT. When the voltage V.sub.REF becomes smaller than the voltage V.sub.INT, for instance, due to the increase of the internal voltage V.sub.INT caused by the increase of the supply voltage Ext.Vcc or other reasons, the conductivity of the PMOS transistor 22b decreases. Correspondingly, the potential at the drain of the PMOS transistor 22b decreases, and thus the conductivity of the NMOS transistor 22c decreases. Consequently, the potential at the drain of the NMOS transistor 22c increases, resulting in reduction of the conductivity of the output transistor 23. Accordingly, the internal voltage V.sub.V.sub.INT decreases to the same value as the voltage V.sub.REF (V.sub.INT =V.sub.REF). Conversely, if the internal voltage V.sub.INT decreases smaller than the reference voltage V.sub.REF (V.sub.REF &gt;V.sub.INT) controlling is carried out in a manner contrary to the above, and thus the internal voltage V.sub.INT is stably maintained at the reference voltage V.sub.REF.
As described above, the internal stepdown circuit in FIG. 5 generates the internal voltage V.sub.INT independent of the supply voltage Ext.Vcc. This internal voltage V.sub.INT is applied to respective internal circuits in the semiconductor integrated circuit device.
When the semiconductor integrated circuit device provided with the internal stepdown circuit 2 in FIG. 5 is in a standby condition, the clock signal .phi. is at the "H" level and the PMOS transistor 21a is maintained in an OFF state. Consequently, the current quantity supplied from the current quantity switching circuit 21 to the voltage comparator circuit 22 is reduced, resulting in reduction of the consumption power in the standby mode.
As described above, the internal stepdown circuit of the prior art shown in FIG. 5 is intended to reduce the consumption power in the standby mode by setting the PMOS transistor 21a at the OFF state in the standby mode. However, even when the PMOS transistor 21a is turned off, a current is supplied to the voltage comparator circuit 22 in the standby mode through the PMOS transistor 21b, because this PMOS transistor 21b is turned on. Further, the internal stepdown circuit of the prior art shown in FIG. 5 has structures in which the current flows in the reference voltage generator circuit 1 even in the standby mode.
Therefore, the internal stepdown circuit of the prior art shown in FIG. 5 still has a serious problem that the consumption power cannot be sufficiently reduced.